The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of integrated circuit evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling-down also produces a relatively high power dissipation value, which may be addressed by using low power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. These devices may then be packaged and sold as IC chips.
As technologies continue to advance, often times IC chips are used in a high frequency environment, such as a radio frequency (RF) environment. In addition, as the semiconductor devices get smaller and the functionalities of the chips continue to increase, an IC chip may have a small area and yet have many input and output (I/O) pins operable to control and program the IC chip. Consequently, the pitch size—or the distance between the pins—becomes smaller as well. Current technologies may not meet the simultaneous demands of establishing proper electrical connections to all the pins of an IC chip having a small pitch size and testing the IC chip's high frequency response characteristics. Accordingly, a method and device to efficiently and effectively test the high frequency response characteristics of an IC chip having a small pitch size is needed.